1. Field of the Invention
This invention relates to a semiconductor device, a semiconductor integrated circuit and a bump resistance measurement method wherein the connection resistance of an internal bump or main bump for connecting two semiconductor chips can be measured for each bump.
2. Description of the Related Art
In recent years, introduction of a system (SiP: System in Package) single-packaged or a system modularized using a semiconductor technique has been and is proceeding rapidly together with downsizing of an electronic apparatus. A plurality of semiconductor chips are mounted on a mounting substrate of the package.
On the other hand, the system includes a plurality of circuit blocks which handle different signals from each other such as an analog circuit section and a digital circuit section. Further, different performances such as a high speed or a low speed and a high frequency or a low frequency are required for the different circuit blocks. Therefore, it is generally difficult to use a common process to fabricate, at a low cost, a system which satisfies all of the required performances at a high level. However, if packaging is merely performed for each circuit block, then downsizing of an electronic apparatus cannot be achieved. Therefore, it is necessary to incorporate a plurality of chips in one package or one module and interconnect the chips directly.
However, the number of connections between chips is increasing from a reason of multi-functionalization of electronic apparatus and so forth, and downsizing of a connecting portion is required essentially. Therefore, it has been begun to really utilize bumps in place of wire bonds.
Upon bump connection, wiring lines are sometimes wired only between chips without extending to the outside of the SiP. Or, bump connection may assume a CoC (Chip on Chip) connection scheme wherein a plurality of chips are layered in order to implement downsizing of the outer profile of the package. A bump for such connection between chips is generally called “internal bump” in order to distinguish the same from a bump for external connection of the package.
Normally, a small chip or second chip having a high performance is placed on and bump-connected to a large chip or first chip.
For example, a main signal processing LSI is a single chip on which a logic circuit and a DRAM (Dynamic Random Access Memory) are mounted together. While the logic circuit has a high processing speed and requires use of an advanced process, the DRAM does not require a very high processing speed and it does not make a problem even if an expensive advanced process is not used for the DRAM. In other words, where a DRAM and a logic circuit are individually mounted on chips separate from each other and fabricated by different production processes, a system can be produced at a cost lower than that required where a system is produced using a chip on which a DRAM and a logic circuit are mounted together.
In particular, the DRAM is produced using an old low-cost process while the logic circuit is produced using a head process. If a DRAM chip as a second chip is placed on and connected to a completed logic chip as a first chip through a bump to implement a CoC structure, then the cost can be reduced totally.
Conversely, the second chip to be mounted on the first chip may be fabricated using a special process of a high-performance and hence at an increased cost. In this instance, the degree of integration of the second chip is raised as high as possible to achieve downsizing.
Therefore, the CoC structure includes a great number of internal bump connections whose diameter is approximately several tens μm.
Several hundreds to several thousands bump arrays are formed in advance on the first chip to be used as a base, and the second chip is placed on the first chip with a connecting face thereof positioned with respect to first chip. In this state, the first and second chips are heated so as to be contact bonded to each other. However, at this time, a bump may possibly be connected in a displaced relationship to the second chip or a cavity may be produced within a bump because of deviation of a condition or the like. Therefore, while a great number of products are fabricated using the same fabrication apparatus, a package may be produced in a state wherein such a bump connection portion whose reliability is low as just described is mixed in several hundreds to several thousands bumps per one package.
In order to prevent failure of bump connection, it is significant to achieve both of stabilization of fabrication and development of a screening method.
Even if connection of an internal bump in the CoC structure is established but incompletely, if the connection is somewhat sufficient, normal function and operation are allowed. However, there is the possibility that, when a product having such poor connection is placed actually in the market and is acted upon by a mechanical stress or the like, the connection may be cancelled completely thereby disabling the product. Therefore, in order to perform the screening for such products, it is necessary to diagnose the degree of completeness of connections. To this end, it is necessary to measure the connection resistance of the bumps and screen those products whose connection resistance has a certain value or more.
As a method for detecting connection failure of internal bumps, a method has been proposed and is disclosed in Japanese Patent Laid-Open No. 2003-185710 (hereinafter referred to as Patent Document 1). In the method, a switch capable of connecting bumps to each other along a single resistance measurement path is provided on both of a semiconductor chip on the base side and another semiconductor chip to be mounted on the base side semiconductor chip. Further, the resistance value of the bump connection path is measured to detect whether or not a failed connection portion exists.